Volatile programmable devices, such as FPGAs, typically rely on external storage media to hold the bitstreams used to configure the devices. For example, programmable read-only memory (PROM) devices are often used to hold the configuration bitstreams for FPGAs. Such devices are referred to as “boot PROMs,” because they are used to boot (i.e., initialize) programmable devices, such as volatile FPGAs.
FIG. 1 shows a block diagram of one conventional architecture for configuring an FPGA 102 in which a parallel PROM device 104 is used as the boot PROM. As shown in FIG. 1, for a typical FPGA having about 8 million bits of configuration data, a (disadvantageously large) total of 29 FPGA pins are dedicated to this configuration architecture (i.e., 1 pin for the chip select signal (/CS), one pin for the configuration clock signal (SCLK), eight pins for data, and 19 pins for addressing). Another disadvantage of this solution is the relatively large package size of parallel PROMs, which require a relatively larger amount of PCB board space.
FIG. 2 shows a block diagram of another conventional architecture for configuring an FPGA 202 using a parallel PROM 204 as the boot PROM, in which a controller 206 (e.g., a complex programmable logic device (CPLD) or a micro-controller) provides an interface between the parallel PROM and the FPGA. In order to reduce the number of pins consumed on the FPGA, controller 206 handles the addressing into PROM 204 and converts the parallel data received from PROM 204 into serial data for transmission to FPGA 202 via a single FPGA pin (DIN).
FIG. 3 shows a block diagram of yet another conventional architecture for configuring an FPGA 302, in this case, using a serial PROM 304 as the boot PROM, where a micro-controller 306 forms the interface between the PROM and the FPGA. In one possible implementation, serial PROM 304 is a non-volatile serial flash PROM that interfaces with an industry-standard Serial Peripheral Interface (SPI) on micro-controller 306.
Although these controller-based solutions of FIGS. 2 and 3 reduce the number of FPGA pins consumed, they do so at the increased cost of having to provide two chips to configure an FPGA: one chip for the memory device and one chip for the controller.
Companies, such as Atmel Corporation of San Jose, Calif., manufacture serial PROM devices as FPGA configuration devices that interface directly to FPGAs (i.e., without an intermediary controller); however, these non-standard serial PROMs are proprietary and therefore typically more expensive than standard serial PROMs.